Such non-volatile memory structures are e.g. known in the art as flash memory devices, whereby the memory function is implemented by storing electrical charges on memory cells known as floating gates. Two well known types of such flash memory devices are NAND flash and NOR flash. There is a constant pressure to make cheaper memory devices with a higher storage capacity, which is a.o. addressed by constant miniaturization, different memory topologies, better process and yield control. Particularly relevant for the present invention are memory cell structures with a floating gate having an inverted T shape.
US20060292802 describes a NAND flash memory device and a method for forming the same. The memory structure comprises elements with an inverted T shape, fabricated from box-shaped parts, the sides of which are narrowed by etching. A disadvantage of the method used in US20060292802 is that the process is complex and extra process steps are needed to prevent etching damage.
US20080074920 describes a 2-dimensional non-volatile memory array, wherein each memory cell comprises a floating gate, the floating gate having an inverted T shape in cross section. Methods are described to form these inverted T shapes, whereby a first floating gate layer is deposited on top of a dielectric layer, to form the lower (horizontal) side of the inverted T shape, and a second floating gate layer, forming the upright (vertical) part of the floating gate, is deposited on top of the first floating gate layer. In a first method, the upright part of the floating gate is formed by filling slots between sidewall spacers formed against masking portions deposited on top of the first floating gate layer. In a second method, the upright part of the floating gate is formed by filling slots between sidewall spacers formed against Shallow Trench Isolation (STI) structures, extending above the active areas. In a third method masking portions on a floating gate layer establish a pattern for partially etching the floating gate layer thereby forming the upright (vertical) part. The outer surface of the etched floating gate layer is then oxidized, and then the oxide layer is used as sidewall spacers to form STI trenches to define the individual memory cells. A disadvantage of the methods described in US20080074920 is that the methods to form inverted T shapes are complex, and require many process steps.